@T4V0 Hello, I've been doing a lot of research on this project these days and I've brought the code to a better level, I hope... But I'm not sure if this simulation...
This is VHDL code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Kitchen_Timer is
port (
clk : in std_logic; -- Clock input
reset : in std_logic; -- Reset input
start : in std_logic; -- Start button input
stop : in std_logic; -- Stop button input
adjust_interval_up : in std_logic; -- Button for increasing alarm interval
adjust_interval_down : in std_logic; -- Button for decreasing alarm interval
alarm : out std_logic -- Alarm output
);
end entity Kitchen_Timer;
architecture Behavioral of Kitchen_Timer is
signal count : integer range 0 to 3600000 := 0; -- Adjust range for 1 hour
signal alarming : std_logic := '0';
signal alarm_interval : integer range 600 to 3600000 := 600; -- Adjust range for 1 hour