library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Kitchen_Timer is
port
(
clk : in std_logic; -- Clock input
reset : in std_logic; -- Reset input
start : in std_logic; -- Start button input
stop : in std_logic; -- Stop button input
adjust_interval_up : in std_logic; -- Button for increasing alarm interval
adjust_interval_down : in std_logic; -- Button for decreasing alarm interval
alarm : out std_logic -- Alarm output
);
end entity Kitchen_Timer;
architecture Behavioral of Kitchen_Timer is
signal count : integer range 0 to 60 := 0; -- Adjust range for 1 hour
signal alarming : std_logic := '0';
signal alarm_interval : integer range 1 to 60 := 1; -- Adjust range for 1 hour
begin
process (clk, reset)
begin
if reset = '1' then
count <= 0;
alarm_interval <= 1;
elsif rising_edge(clk) then
if start = '1' then
count <= count + 1;
end if;
if stop = '1' then
count <= 0;
alarming <= '0';
end if;
if count = alarm_interval then
alarming <= '1';
end if;
if adjust_interval_up = '1' then
if alarm_interval < 60 then
alarm_interval <= alarm_interval + 1; -- Adjust increment for 1 minute
end if;
count <= 0; -- Reset count when adjusting interval
elsif adjust_interval_down = '1' then
if alarm_interval > 60 then
alarm_interval <= alarm_interval - 1; -- Adjust decrement for 1 minute
end if;
count <= 0; -- Reset count when adjusting interval
end if;
end if;
end process;
alarm <= alarming;
end architecture Behavioral;
tb_Kitchen_Timer.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_Kitchen_Timer is
end tb_Kitchen_Timer;
architecture tb of tb_Kitchen_Timer is
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal start : std_logic := '0';
signal stop : std_logic := '0';
signal adjust_interval_up : std_logic := '0';
signal adjust_interval_down : std_logic := '0';
signal alarm : std_logic;
constant TbPeriod : time := 10 ns;
signal TbClock : std_logic := '0';
signal TbSimEnded : std_logic := '0';
begin
dut : entity work.Kitchen_Timer
port map
(
clk => clk,
reset => reset,
start => start,
stop => stop,
adjust_interval_up => adjust_interval_up,
adjust_interval_down => adjust_interval_down,
alarm => alarm
);
-- Clock generation
TbClock <= not TbClock after TbPeriod/2 when TbSimEnded /= '1' else '0';
-- EDIT: Check that clk is really your main clock signal
clk <= TbClock;
stimuli : process
variable num_ticks : natural;
begin
-- Reset generation
reset <= '1';
wait for 20 ns;
reset <= '0';
wait for 20 ns;
-- Start the timer
start <= '1';
wait for 20 ns;
start <= '0';
stop <= '1';
-- Adjust interval up and down
adjust_interval_up <= '1';
wait for 10 ns;
start <= '1';
stop <= '0';
adjust_interval_up <= '0';
wait for 30 ns;
start <= '0';
stop <= '1';
adjust_interval_down <= '1';
wait for 10 ns;
start <= '1';
stop <= '0';
adjust_interval_down <= '0';
wait for 20 ns;
start <= '0';
stop <= '1';
adjust_interval_up <= '1';
wait for 600 ns;
start <= '1';
stop <= '0';
adjust_interval_up <= '0';
-- Wait for the timer to reach the alarm interval (60 clocks)
wait for 600 ns; -- Simulate for the required time
-- Stop the timer
start <= '0';
stop <= '1';
wait for 100 ns;
-- Stop the clock and terminate the simulation
TbSimEnded <= '1';
wait;
end process;
end tb;
This should be easier to simulate, I've included a simulation done with Questa.