Is the 1/60 Hz set somewhere or is it set in the code itself?
You would set that on the testbench or on your synthesis code, but that is unnecessary, I only said that in case if you tested it on a actual FPGA. If you do that on your testbench, it would take a very long time to simulate.
When you say that I must have an "alarming" signal on the simulation, is it actually this "alarm" signal that is presented on the simulation or?
The alarm signal. The "alarming" is when the alarm signal is in a high logic state.
And, do I need to have count signal in simulation?
I wouldn't say it's mandatory, but it is a good addition to the simulation, keep it.