T4V0, hace 9 meses

@dejo Whoops, I made a mistake, you don't need to include the entity when simulating. This line bellow should be the correct one:

add wave -label "count" -radix unsigned /dut/count

This is my .do file (when using Modelsim or Questa, change to the directory with all the .vhd files and the .do file and execute the command do tb.do):

tb.do

#Creates project's library
vlib work

#Compiles project with VHDL93 standard: all files used in the testbench. They should be compiled in order of dependency.
vcom -93 Kitchen_Timer.vhd testbench.vhd

#Simulates (work is the directory, tb_Kitchen_Timer is the entity's name).
#The argument -voptargs="+acc" is necessary to disable signal optimization in Questa.
vsim -voptargs="+acc" -t ns work.tb_Kitchen_Timer

#Show waveforms.
view wave

#Add specific signals.
# -radix: binary, hex, dec, unsigned.
# -label: wave's name.
add wave -label "clk" -radix binary /clk
add wave -label "reset" -radix binary /reset
add wave -label "start" -radix binary /start
add wave -label "stop" -radix binary /stop
add wave -label "adjust_interval_up" -radix binary /adjust_interval_up
add wave -label "adjust_interval_down" -radix binary /adjust_interval_down
add wave -label "alarm" -radix binary /alarm
add wave -label "count" -radix unsigned /dut/count
add wave -label "TbClock" -radix binary /TbClock
add wave -label "TbSimEnded" -radix binary /TbSimEnded

#Simulate for 1500 ns.
run 1500ns

# Zoom to fit entire window.
wave zoomfull
write wave wave.ps

I've also included the simulation result.